The Restoration of the PDP-8/I Minicomputer (PAGE 14)
Diagnosing the TTY input section.
I suspect that the signals on my home-built W076 might be inverted, so to test that
theory I wrote a little test program that reads
characters and keeps count in the MQ of the number of characters that have been read.
Sure enough, even when the serial line is idle, the MQ increments, indicating that characters
are constantly being read. This suggests that I got the sense of the TTY Input on the W076
wrong and need to invert it.
After inverting the signals, the same thing happens except that I don't even get
the garbage in the AC -- but the MQ increments at what looks like 15 cps (I boosted the
baud rate to 150 baud).
So, I suspect that of the three TTY Receiver cards I have, not one of them works (one shows characters
arriving at 15 cps when there are no characters being sent, another shows character arriving about 8X faster again with no characters being sent,
and the third doesn't receive characters at all). Whee!
And to top it all off, I just got a stuck bit in the memory subsystem; I can't deposit a zero into position 2 (i.e., the 2000 bit).
Again with the "whee!" Diagnosed this to be the MB in the M220 card; replaced the flip-flop, no change, so next replaced
the 7440 buffer at E7, fixed. :-) That wasn't too bad...
In this picture, you can see the HP-1600A Logic State Analyzer that I recently acquired and that I use to
diagnose problems with the 8/I. In the picture, I've captured the first part of the problem with the M706
serial receiver card. The HP-1600A is connected to a 7474 flip-flop, with the pins connected in order (the display
shows signals in the order (left to right) 15 through 0, signals 15, 14, 7, and 0 are not connected to the 7474).
Notice how in the highlighted line (9th from the top) pins 8 and 9 (the output of the flip-flop) have changed state
without any of the other pins changing state. This is slightly misleading, because the logic state
analyzer only samples the state of the pins when the clock changes state -- this problem actually occurred between
clock signals when the preset line was asserted.
This just gives a "big picture" view of my lab environment in the basement. These pages were becoming rather
dry so I figured some nice pictures were in order :-) The oscilloscope under the logic state analyzer is an HP-1222A
that I got at an auction years ago.
Just in time for the holidays! Everything is fixed now; we repaired the M706 TTY receiver card, and found the
flaky memory (it turned out to be a dead 2N3009 transistor on the M310@A21 -- replaced with a 2N3904). The M706 problem was a dead
7474 flip-flop chip on the ACTIVE/IN LAST UNIT.
So, now that everything seems to work, it's time to start with the MAINDEC diagnostics.
Not being content with 110 baud (nor 150 baud), I used the Caglec 452 from the PDP-12 and boosted the baud rate to 9600.
Chess (in RIM format, at that!) loads in about 15 seconds :-)